Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

Xiaoyu Sun, Rui Liu, Yi Ju Chen, Hsiao Yun Chiu, Wei Hao Chen, Meng Fan Chang, Shimeng Yu

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1-0.55 V (or 0.5 V) with a bit error rate ∼0.23% (or ∼1.56%), which only introduced ∼0.08% (or ∼1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than 8× (or 10×).

Original languageEnglish (US)
Article number7995135
Pages (from-to)2962-2965
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
StatePublished - Oct 2017


  • Binary synapses
  • classification
  • low power
  • neural network
  • static random access memory (SRAM)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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