Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Xuejue Huang; Phillip Restle; Thomas Bucelot; Yu Cao; Tsu Jae King

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, Tsu Jae King

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

Original language	English (US)
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Pages	19-22
Number of pages	4
State	Published - 2002
Externally published	Yes
Event	IEEE 2002 Custom Integrated Circuits Conference - Orlando, FL, United States Duration: May 12 2002 → May 15 2002

Other

Other	IEEE 2002 Custom Integrated Circuits Conference
Country/Territory	United States
City	Orlando, FL
Period	5/12/02 → 5/15/02

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@inproceedings{d64c60caeed645b18e81a8732015b819,

title = "Loop-based interconnect modeling and optimization approach for multi-GHz clock network design",

abstract = "An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.",

author = "Xuejue Huang and Phillip Restle and Thomas Bucelot and Yu Cao and King, {Tsu Jae}",

year = "2002",

language = "English (US)",

pages = "19--22",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "IEEE 2002 Custom Integrated Circuits Conference ; Conference date: 12-05-2002 Through 15-05-2002",

}

TY - GEN

T1 - Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

AU - Huang, Xuejue

AU - Restle, Phillip

AU - Bucelot, Thomas

AU - Cao, Yu

AU - King, Tsu Jae

PY - 2002

Y1 - 2002

N2 - An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

AB - An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

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UR - http://www.scopus.com/inward/citedby.url?scp=0036045268&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0036045268

SP - 19

EP - 22

BT - Proceedings of the Custom Integrated Circuits Conference

T2 - IEEE 2002 Custom Integrated Circuits Conference

Y2 - 12 May 2002 through 15 May 2002

ER -

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Abstract

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ASJC Scopus subject areas

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