Leakage minimization of digital circuits using gate sizing in the presence of process variations

Sarvesh Bhardwaj, Sarma Vrudhula

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


This paper presents a novel gate-sizing methodology to minimize the leakage power in the presence of process variations. The method is based on modeling the statistics of leakage and delay as posynomials functions to formulate a geometricprogramming problem. The existing statistical leakage model is extended to include the variations in gate sizes, as well as systematic variations. Using a simplified delay model, we propose an efficient method to evaluate the α-percentile of path delays without enumerating the paths in a circuit. The complexity of evaluating the objective function of the optimization problem is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with \N| gates and \E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. The statistical optimization methodology is shown to provide as much as 15% reduction in the mean leakage power as compared to traditional worst case gate sizing with the same delay constraints.

Original languageEnglish (US)
Article number4454006
Pages (from-to)445-455
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number3
StatePublished - Mar 2008


  • Circuit optimization
  • Leakage power
  • Process variations

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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