Impact of sampling clock phase noise on ΣΔ frequency discriminators

Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.