High Performance Pipe-lined Architecture for Open FEC Encoder

Open forward error correction (oFEC) schemes have been considered as one of the potential candidates for FEC schemes in optical communication systems, specifically for applications of 800-ZR/ZR+. However, the investigations on the hardware design for oFEC scheme are very limited. Therefore, we propose a novel design for the oFEC encoder in this paper. Instead of performing the encoding process with a massive number of input bits, we propose a pipe-lined mechanism based on the proposed pipe-lined BCH encoding algorithm. This design can be adopted to different designs with different throughput requirements by changing the parallelism factor. We also conduct implementations on a Xilinx Virtex UltraScale+ VU19P FPGA board. The results show that the proposed encoder design can achieve a throughput of about 47 Gbps. Furthermore, the proposed encoder can be re-designed to achieve a throughput of around 188 Gbps by applying a higher parallelism factor, without an increase in the size of buffer memories.