Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

E. Aykut Dengi; Ronald A. Rohrer

doi:10.1145/266021.266048

Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

E. Aykut Dengi
, Ronald A. Rohrer

Research output: Contribution to journal › Conference article › peer-review

14 Scopus citations

Abstract

A hierarchical two-dimensional field solution technique is introduced for capacitance extraction for VLSI interconnect modeling. As a basis for compromise between the efficiency of Boolean rules-based extraction and the accuracy of flat field solution, this hierarchical approach can handle realistic conductor cross-sections and multiple conformal and/or planarized dielectrics.

Original language	English (US)
Pages (from-to)	127-132
Number of pages	6
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1145/266021.266048
State	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA Duration: Jun 9 1997 → Jun 13 1997

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

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10.1145/266021.266048

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@article{2d91d83b5ec7441799f03ff9ec52364e,

title = "Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling",

abstract = "A hierarchical two-dimensional field solution technique is introduced for capacitance extraction for VLSI interconnect modeling. As a basis for compromise between the efficiency of Boolean rules-based extraction and the accuracy of flat field solution, this hierarchical approach can handle realistic conductor cross-sections and multiple conformal and/or planarized dielectrics.",

author = "Dengi, \{E. Aykut\} and Rohrer, \{Ronald A.\}",

year = "1997",

doi = "10.1145/266021.266048",

language = "English (US)",

pages = "127--132",

journal = "Proceedings - Design Automation Conference",

issn = "0738-100X",

note = "Proceedings of the 1997 34th Design Automation Conference ; Conference date: 09-06-1997 Through 13-06-1997",

}

TY - JOUR

T1 - Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

AU - Dengi, E. Aykut

AU - Rohrer, Ronald A.

PY - 1997

Y1 - 1997

N2 - A hierarchical two-dimensional field solution technique is introduced for capacitance extraction for VLSI interconnect modeling. As a basis for compromise between the efficiency of Boolean rules-based extraction and the accuracy of flat field solution, this hierarchical approach can handle realistic conductor cross-sections and multiple conformal and/or planarized dielectrics.

AB - A hierarchical two-dimensional field solution technique is introduced for capacitance extraction for VLSI interconnect modeling. As a basis for compromise between the efficiency of Boolean rules-based extraction and the accuracy of flat field solution, this hierarchical approach can handle realistic conductor cross-sections and multiple conformal and/or planarized dielectrics.

UR - https://www.scopus.com/pages/publications/0030677634

UR - https://www.scopus.com/pages/publications/0030677634#tab=citedBy

U2 - 10.1145/266021.266048

DO - 10.1145/266021.266048

M3 - Conference article

AN - SCOPUS:0030677634

SN - 0738-100X

SP - 127

EP - 132

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

T2 - Proceedings of the 1997 34th Design Automation Conference

Y2 - 9 June 1997 through 13 June 1997

ER -

Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

Abstract

ASJC Scopus subject areas

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