Hiding cache miss penalty using priority-based execution for embedded processors

Sanghyun Park, Aviral Shrivastava, Yunheung Paek

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can use elaborate techniques like multiple issue, out-of-order execution, speculative execution, value prediction etc. to tolerate high memory latencies, they are often not viable solutions for embedded processors, due to significant area, power and chip complexity overheads. This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors. The compiler classifies the instructions into low-priority and high-priority instructions. The processor executes the high-priority instructions, but delays the execution of low priority instructions. They are executed on a cache miss to hide the cache miss penalty. We empirically evaluate our proposal on the Intel XScale compiler and microarchitecture. Experimental results on benchmarks from Multimedia, MediaBench, MiBench, and SPEC2000 demonstrate an average 17% performance improvements, hiding 75% cache miss penalty.

Original languageEnglish (US)
Title of host publicationDesign, Automation and Test in Europe, DATE 2008
Number of pages6
StatePublished - Aug 25 2008
EventDesign, Automation and Test in Europe, DATE 2008 - Munich, Germany
Duration: Mar 10 2008Mar 14 2008

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


OtherDesign, Automation and Test in Europe, DATE 2008

ASJC Scopus subject areas

  • Engineering(all)


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