TY - GEN
T1 - Fully Digital 1-1 MASH VCO-Based ADC Architecture
AU - Danesh, Mohammadhadi
AU - Sanyal, Arindam
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/8
Y1 - 2019/8
N2 - This paper proposes a novel architecture for purely voltage controlled oscillator (VCO) based 1-1 MASH secondorder analog-to-digital converter (ADC). Each stage of the MASH uses an open loop inverter based ring VCO. The proposed ADC uses phase information from all inverters in the VCO in both the MASH stages to perform efficient multi-bit quantization. A novel VCO quantization error extraction circuit is proposed to easily extract quantization noise of the first VCO stage. A gain calibration for the second stage of the ADC has been analyzed. Behavioral simulations have been performed to validate the proposed architecture.
AB - This paper proposes a novel architecture for purely voltage controlled oscillator (VCO) based 1-1 MASH secondorder analog-to-digital converter (ADC). Each stage of the MASH uses an open loop inverter based ring VCO. The proposed ADC uses phase information from all inverters in the VCO in both the MASH stages to perform efficient multi-bit quantization. A novel VCO quantization error extraction circuit is proposed to easily extract quantization noise of the first VCO stage. A gain calibration for the second stage of the ADC has been analyzed. Behavioral simulations have been performed to validate the proposed architecture.
UR - http://www.scopus.com/inward/record.url?scp=85074988281&partnerID=8YFLogxK
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U2 - 10.1109/MWSCAS.2019.8884925
DO - 10.1109/MWSCAS.2019.8884925
M3 - Conference contribution
AN - SCOPUS:85074988281
T3 - Midwest Symposium on Circuits and Systems
SP - 501
EP - 504
BT - 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019
Y2 - 4 August 2019 through 7 August 2019
ER -