Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels

Chen Ling Chou, Umit Y. Ogras, Radu Marculescu

Research output: Contribution to journalArticlepeer-review

162 Scopus citations


Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known apriori. This paper targets real-time applications which are dynamically mapped onto embedded MPSoCs, where communication happens via the Network-on-Chip (NoC) approach, and resources connected to the NoC have multiple voltage levels. We address precisely the energy- and performance-aware incremental mapping problem for NoCs with multiple voltage levels and propose an efficient technique (consisting of region selection and node allocation) to solve it. Moreover, the proposed technique allows for new applications to be added to the system with minimal interprocessor communication overhead. Experimental results show that the proposed technique is very fast, and as much as 50% communication energy savings can be achieved compared to using an arbitrary allocation scheme.

Original languageEnglish (US)
Article number4627545
Pages (from-to)1866-1879
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number10
StatePublished - Oct 2008
Externally publishedYes


  • Low-power design
  • Multiprocessor interconnection
  • Networks on Chip (NoCs)
  • Optimization methods
  • Real-time systems

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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