Efficient generation of delay change curves for noise-aware static timing analysis

K. Agarwal; Yu Cao; T. Sato; D. Sylvester; Chenming Hu

doi:10.1109/ASPDAC.2002.994889

Efficient generation of delay change curves for noise-aware static timing analysis

K. Agarwal
, Yu Cao
, T. Sato
, D. Sylvester
, Chenming Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Scopus citations

Abstract

In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on any victim/aggressor configuration. Such an approach captures important noise considerations such as the possibility of delay change even when the switching windows of neighboring gates do not overlap. The technique is model-independent, which we demonstrate by using several crosstalk noise models to obtain results. Furthermore, we extend an existing noise model to more accurately handle multiple aggressors in the timing analysis framework. DCC results from the analytical approach closely match those from time-consuming SPICE simulations, making timing analysis using DCCs efficient as well as accurate.

Original language	English (US)
Title of host publication	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	77-84
Number of pages	8
ISBN (Electronic)	0769514413, 9780769514413
DOIs	https://doi.org/10.1109/ASPDAC.2002.994889
State	Published - 2002
Externally published	Yes
Event	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India Duration: Jan 7 2002 → Jan 11 2002

Publication series

Name	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Other

Other	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Country/Territory	India
City	Bangalore
Period	1/7/02 → 1/11/02

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2002.994889

Cite this

Agarwal, K., Cao, Y., Sato, T., Sylvester, D., & Hu, C. (2002). Efficient generation of delay change curves for noise-aware static timing analysis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 77-84). Article 994889 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994889

Efficient generation of delay change curves for noise-aware static timing analysis. / Agarwal, K.; Cao, Yu; Sato, T. et al.
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 77-84 994889 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Agarwal, K, Cao, Y, Sato, T, Sylvester, D & Hu, C 2002, Efficient generation of delay change curves for noise-aware static timing analysis. in Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 994889, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Institute of Electrical and Electronics Engineers Inc., pp. 77-84, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, India, 1/7/02. https://doi.org/10.1109/ASPDAC.2002.994889

Agarwal K, Cao Y, Sato T, Sylvester D, Hu C. Efficient generation of delay change curves for noise-aware static timing analysis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 77-84. 994889. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). doi: 10.1109/ASPDAC.2002.994889

Agarwal, K. ; Cao, Yu ; Sato, T. et al. / Efficient generation of delay change curves for noise-aware static timing analysis. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 77-84 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

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AB - In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on any victim/aggressor configuration. Such an approach captures important noise considerations such as the possibility of delay change even when the switching windows of neighboring gates do not overlap. The technique is model-independent, which we demonstrate by using several crosstalk noise models to obtain results. Furthermore, we extend an existing noise model to more accurately handle multiple aggressors in the timing analysis framework. DCC results from the analytical approach closely match those from time-consuming SPICE simulations, making timing analysis using DCCs efficient as well as accurate.

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Efficient generation of delay change curves for noise-aware static timing analysis

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