Design and analysis of LDPC decoders for software defined radio

Sangwon Seo; Trevor Mudge; Yuming Zhu; Chaitali Chakrabarti

doi:10.1109/SIPS.2007.4387546

Design and analysis of LDPC decoders for software defined radio

Sangwon Seo, Trevor Mudge, Yuming Zhu, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

28 Scopus citations

Abstract

Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

Original language	English (US)
Title of host publication	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages	210-215
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2007.4387546
State	Published - 2007
Event	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China Duration: Oct 17 2007 → Oct 19 2007

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Other

Other	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Country/Territory	China
City	Shanghai
Period	10/17/07 → 10/19/07

Keywords

LDPC
Min-sum iterative decoding
SDR
SIMD
SODA

ASJC Scopus subject areas

Media Technology
Signal Processing

Access to Document

10.1109/SIPS.2007.4387546

Cite this

Design and analysis of LDPC decoders for software defined radio. / Seo, Sangwon; Mudge, Trevor; Zhu, Yuming et al.
2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings. 2007. p. 210-215 4387546 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Seo, S, Mudge, T, Zhu, Y & Chakrabarti, C 2007, Design and analysis of LDPC decoders for software defined radio. in 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings., 4387546, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 210-215, 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Shanghai, China, 10/17/07. https://doi.org/10.1109/SIPS.2007.4387546

@inproceedings{7cbefe3afd604570b5b2b2bbf05a4ea5,

title = "Design and analysis of LDPC decoders for software defined radio",

abstract = "Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.",

keywords = "LDPC, Min-sum iterative decoding, SDR, SIMD, SODA",

author = "Sangwon Seo and Trevor Mudge and Yuming Zhu and Chaitali Chakrabarti",

year = "2007",

doi = "10.1109/SIPS.2007.4387546",

language = "English (US)",

isbn = "1424412226",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "210--215",

booktitle = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings",

note = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 ; Conference date: 17-10-2007 Through 19-10-2007",

}

TY - GEN

T1 - Design and analysis of LDPC decoders for software defined radio

AU - Seo, Sangwon

AU - Mudge, Trevor

AU - Zhu, Yuming

AU - Chakrabarti, Chaitali

PY - 2007

Y1 - 2007

N2 - Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

AB - Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

KW - LDPC

KW - Min-sum iterative decoding

KW - SDR

KW - SIMD

KW - SODA

UR - http://www.scopus.com/inward/record.url?scp=47949118113&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47949118113&partnerID=8YFLogxK

U2 - 10.1109/SIPS.2007.4387546

DO - 10.1109/SIPS.2007.4387546

M3 - Conference contribution

AN - SCOPUS:47949118113

SN - 1424412226

SN - 9781424412228

T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SP - 210

EP - 215

BT - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings

T2 - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007

Y2 - 17 October 2007 through 19 October 2007

ER -

Design and analysis of LDPC decoders for software defined radio

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this