Abstract
Chip integration of dielectric thin films with low leakage currents, high dielectric strengths, and high permittivities will be. required for the memory cells of ULSI DRAM’s, and power supply decoupling in high-speed ULSI packages. Due to the numerous advantages of cubic paraelectric materials over their ferroelectric counterparts, we have studied polycrystalline paraelectric perovskite thin films in the Pb-La-Ti-O or PLT (28 mol % La) system. Thin (0.5 μm) films were integrated onto 3-in Pt/Ti/SiO2/(100) Si wafers by the sol-gel processing technique. Low-field dielectric measurements yielded dielectric permittivity (Ñ”r) and loss tangent (tan 5) of 1400 and 0.015, respectively, while high-field Sawyer-Tower measurements {P-E) showed linear behavior (with Ñ”r~ 1400) up to 40 kV/cm, which approached saturation (with Ñ”r ~ 850) at 200 kV/cm. Pulse charging transient (I-t) and current-voltage (I-V) measurements indicated a high charge storage density (15.8 pC/cm2) and low leakage current density (0.50 μA/cm2) under a field of 200 kV/cm. The charging time for a 1-pm2 PLT capacitor at 200 kV/cm was estimated to be 0.1 ns. The preliminary data demonstrate that paraelectric PLT thin films have excellent potential for use in ULSI DRAM’s and as decoupling capacitors.
Original language | English (US) |
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Pages (from-to) | 1607-1613 |
Number of pages | 7 |
Journal | IEEE Transactions on Electron Devices |
Volume | 39 |
Issue number | 7 |
DOIs | |
State | Published - Jul 1992 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering