TY - GEN
T1 - Built-In Self-Test Measurement of Single Event Transients in the Skywater S90ln 90 Nm Process
AU - Westfall, S.
AU - Loveless, T. D.
AU - Carpenter, J. L.
AU - Peyton, T.
AU - Kim, J.
AU - Barnaby, H. J.
AU - Neuendank, J.
AU - Nour, M.
AU - Manos, P.
AU - Chambers, M.
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Heavy-ion-induced single-event transients (SET) in combinational logic gates fabricated in the SkyWater S90LN 90 nm bulk CMOS process are measured experimentally using programmable built-in self-test (BIST) circuits. Four BIST circuits, differing only in the type of combinational logic gates, were simultaneously irradiated at the Lawrence Berkeley National Laboratory 88' Cyclotron facility using the 16 MeV amu ion cocktail and a range of linear energy transfer (LET) values. The median SET pulse widths for minimally-sized inverters and those up to 3 x the minimum drive strength range between 70 and 630 ps, whereas the minimally-sized two-input NAND gates showed median pulse widths between 210 ps and 960 ps for LET values up to 67 MeV-cm2mg. For LET values of 30 MeV-cm2mg or less, nearly all SET pulse widths are contained to within 1 ns, with the maximum SET pulse width being 1.96 ns for the two-input NAND gates measured at 67 MeV-cm2mg. Further, cross-sections tend to be inversely proportional to drive strength, as expected.
AB - Heavy-ion-induced single-event transients (SET) in combinational logic gates fabricated in the SkyWater S90LN 90 nm bulk CMOS process are measured experimentally using programmable built-in self-test (BIST) circuits. Four BIST circuits, differing only in the type of combinational logic gates, were simultaneously irradiated at the Lawrence Berkeley National Laboratory 88' Cyclotron facility using the 16 MeV amu ion cocktail and a range of linear energy transfer (LET) values. The median SET pulse widths for minimally-sized inverters and those up to 3 x the minimum drive strength range between 70 and 630 ps, whereas the minimally-sized two-input NAND gates showed median pulse widths between 210 ps and 960 ps for LET values up to 67 MeV-cm2mg. For LET values of 30 MeV-cm2mg or less, nearly all SET pulse widths are contained to within 1 ns, with the maximum SET pulse width being 1.96 ns for the two-input NAND gates measured at 67 MeV-cm2mg. Further, cross-sections tend to be inversely proportional to drive strength, as expected.
UR - https://www.scopus.com/pages/publications/105008491726
UR - https://www.scopus.com/pages/publications/105008491726#tab=citedBy
U2 - 10.1109/RADECS61975.2024.11017554
DO - 10.1109/RADECS61975.2024.11017554
M3 - Conference contribution
AN - SCOPUS:105008491726
T3 - 2024 RADECS Data Workshop, RADECS 2024 in conjunction with the 2024 RADECS Conference
BT - 2024 RADECS Data Workshop, RADECS 2024 in conjunction with the 2024 RADECS Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 RADECS Data Workshop, RADECS 2024
Y2 - 19 September 2024
ER -