Boosting the accuracy of analog test coverage computation through statistical tolerance analysis

S. Ozev, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize onchip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.

Original languageEnglish (US)
Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PublisherIEEE Computer Society
Number of pages7
ISBN (Electronic)0769515703
StatePublished - Jan 1 2002
Externally publishedYes
Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
Duration: Apr 28 2002May 2 2002

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other20th IEEE VLSI Test Symposium, VTS 2002
Country/TerritoryUnited States


  • Analog circuits
  • Analog computers
  • Boosting
  • Circuit faults
  • Circuit testing
  • Computational efficiency
  • Signal analysis
  • Signal generators
  • System testing
  • Tolerance analysis

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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