Behavioral synthesis of field programmable analog array circuits

This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and post placement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacitor values due to the limited set of allowable values in an FPAA. For the placement and routing step, an efficient method to estimate the circuit performance degradation due to parasitic effects is given. Using performance degradation as the cost function, an algorithm for finding an optimal FPAA placement and routing configuration is given. The efficacy of the methods developed is demonstrated by direct measurements on a set of filters.