Analytical performance models for NoCs with multiple priority traffic classes

Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Umit Y. Ogras

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


Networks-on-chip (NoCs) have become the standard for interconnect solutions in industrial designs ranging from client CPUs to many-core chip-multiprocessors. Since NoCs play a vital role in system performance and power consumption, pre-silicon evaluation environments include cycle-accurate NoC simulators. Long simulations increase the execution time of evaluation frameworks, which are already notoriously slow, and prohibit design-space exploration. Existing analytical NoC models, which assume fair arbitration, cannot replace these simulations since industrial NoCs typically employ priority schedulers and multiple priority classes. To address this limitation, we propose a systematic approach to construct priority-aware analytical performance models using micro-architecture specifications and input traffic. Our approach decomposes the given NoC into individual queues with modified service time to enable accurate and scalable latency computations. Specifically, we introduce novel transformations along with an algorithm that iteratively applies these transformations to decompose the queuing system. Experimental evaluations using real architectures and applications show high accuracy of 97% and up to 2.5× speedup in full-system simulation.

Original languageEnglish (US)
Article numbera52
JournalACM Transactions on Embedded Computing Systems
Issue number5s
StatePublished - Oct 2019


  • NoC performance analysis
  • Priority-based NoC
  • Queuing networks

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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