TY - JOUR
T1 - Analog-Domain Self-Interference Cancellation for Practical Multi-Tap Full-Duplex System
T2 - Theory, Modeling, and Algorithm
AU - Morgenstern, Carl W.
AU - Rong, Yu
AU - Herschfelt, Andrew
AU - Molnar, Alyosha C.
AU - Apsel, Alyssa B.
AU - Landon, David G.
AU - Bliss, Daniel W.
N1 - Publisher Copyright:
© 1983-2012 IEEE.
PY - 2023/9/1
Y1 - 2023/9/1
N2 - Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations.
AB - Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations.
KW - Full-duplex
KW - optimization
KW - outer hull
KW - self-interference cancellation
KW - wireless communications
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U2 - 10.1109/JSAC.2023.3287608
DO - 10.1109/JSAC.2023.3287608
M3 - Article
AN - SCOPUS:85163437796
SN - 0733-8716
VL - 41
SP - 2796
EP - 2807
JO - IEEE Journal on Selected Areas in Communications
JF - IEEE Journal on Selected Areas in Communications
IS - 9
ER -