TY - GEN
T1 - An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays
AU - Kulkarni, Shruti R.
AU - Yin, Shihui
AU - Seo, Jae Sun
AU - Rajendran, Bipin
N1 - Funding Information:
This work was supported in part by the Semiconductor Research Corporation and Cisco.
Funding Information:
B.R. gratefully acknowledges support from IBM through a Faculty Award and support from NJIT where he was employed at the time of this work.
Publisher Copyright:
© 2020 EDAA.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/3
Y1 - 2020/3
N2 - In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STT-RAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ~20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.
AB - In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STT-RAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ~20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.
KW - Neuromorphic hardware
KW - STT-RAM
KW - Spiking Neural Networks
KW - crossbar arrays
UR - http://www.scopus.com/inward/record.url?scp=85087411502&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85087411502&partnerID=8YFLogxK
U2 - 10.23919/DATE48585.2020.9116226
DO - 10.23919/DATE48585.2020.9116226
M3 - Conference contribution
AN - SCOPUS:85087411502
T3 - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
SP - 1019
EP - 1024
BT - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
A2 - Di Natale, Giorgio
A2 - Bolchini, Cristiana
A2 - Vatajelu, Elena-Ioana
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Y2 - 9 March 2020 through 13 March 2020
ER -