An analytical framework with bounded deflection adaptive routing for networks-on-chip

Keyphrases

• Network on chip 100%
• Deflection 100%
• Analytical Framework 100%
• Adaptive Routing 100%
• Routing Algorithm 50%
• Processing Element 33%
• Design Parameters 33%
• Latency 33%
• Communication Traffic 33%
• Energy Consumption 16%
• Performance Improvement 16%
• Embedded Systems 16%
• Chip Design 16%
• Result-oriented 16%
• Resource Allocation 16%
• Latency Constraint 16%
• Traffic Pattern 16%
• Probabilistic Analysis 16%
• Design philosophy 16%
• Communication Architecture 16%
• Simulation Study 16%
• Chip Component 16%
• Case-case 16%
• Chip-based 16%
• Buffer Requirements 16%
• Dynamic Routing 16%
• Network Calculus 16%
• Multi-processor System-on-chip (MPSoC) 16%
• Efficient Routing 16%
• Static Routing 16%
• Average-case 16%
• Link Utilization 16%
• Deadlock 16%
• Link Congestion 16%
• Chip Simulation 16%
• Livelock 16%

Computer Science

• Networks on Chips 100%
• Adaptive Routing 100%
• Routing Algorithm 83%
• Design Parameter 33%
• Processing Element 33%
• Energy Consumption 16%
• Performance Improvement 16%
• Experimental Result 16%
• Traffic Pattern 16%
• Communication Architecture 16%
• Probabilistic Analysis 16%
• Individual Component 16%
• Dynamic Routing 16%
• Network Calculus 16%
• Multi-Processor System-on-Chip 16%
• Link Utilization 16%
• Deadlock 16%
• Embedded System 16%
• Resource Allocation 16%