A VLSI architecture for lifting-based forward and inverse wavelet transform

Kishore Andra, Chaitali Chakrabarti, Tinku Acharya

Research output: Contribution to journalArticlepeer-review

320 Scopus citations


In this paper, we propose an architecture that performs the forward and inverse discrete wavelet transform (DWT) using a lifting-based scheme for the set of seven filters proposed in JPEG2000. The architecture consists of two row processors, two column processors, and two memory modules. Each processor contains two adders, one multiplier, and one shifter. The precision of the multipliers and adders has been determined using extensive simulation. Each memory module consists of four banks in order to support the high computational bandwidth. The architecture has been designed to generate an output every cycle for the JPEG2000 default filters. The schedules have been generated by hand and the corresponding timings listed. Finally, the architecture has been implemented in behavioral VHDL. The estimated area of the proposed architecture in 0.18-μ technology is 2.8 mm square, and the estimated frequency of operation is 200 Mhz.

Original languageEnglish (US)
Pages (from-to)966-977
Number of pages12
JournalIEEE Transactions on Signal Processing
Issue number4
StatePublished - Apr 2002


  • JPEG 2000
  • Lifting
  • VLSI architectures
  • Wavelet transform

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering


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