A sampled-data approach to dc-dc buck converter design

This paper examines the design of digital compensators for high frequency switching dc-dc buck converters. While a high sampling frequency is desirable for digital controllers to minimize intersample effects and recover the performance of the analog compensator (e.g. regulation, robustness with respect input voltage and load fluctuations), finite wordlength effects (i.e. binary approximation/truncation) become more pronounced when faster sampling rates are used. High sampling rates are also accompanied by larger power consumption. When low sampling rates are used, (appropriate truncation algorithms) permit the use of fewer bits to represent compensator coefficients. This reduces final chip area, power consumption, and cost - all very important for application-specific integrated circuit (ASIC) applications. This, however, comes at the expense of performance degradation because of zero-order-hold (ZOH) phase lag and intersample effects. This is a fundamental limitation associated with the traditional two-step design procedure - analog-design followed by conversion-to-digital. While one can compensate for the effects of the ZOH/intersample behavior, direct discrete-time design approach is more systematic. It must be noted, however, that even a direct discrete-time design approach has fundamental limitations. This is because such an approach does not directly take into account intersample behavior. Because of this, the direct design approach may result in unnecessarily (conservatively) high sampling rates. In view of this limitation, we propose the use of direct sampled-data design techniques which use "lifting" concepts that capture the periodic structure of the sampled data system in order to obtain a tractable optimization problem that accommodates meaningful (weighted H^∞) closed loop performance specifications as well as sample rate and intersample behavior. The design obtained is similar to the discretized classical designs complexity-wise - but operates at a much lower sampling rate. FPGA implementation data are presented for each design. Comparisons demonstrating the benefits of the sampled-data approach in achieving reasonable trade-offs are presented. Other issues addressed include: finite word length effects, controller complexity and realization.