A resilience roadmap

Sani R. Nassif, Nikil Mehta, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

80 Scopus citations


Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.

Original languageEnglish (US)
Title of host publicationDATE 10 - Design, Automation and Test in Europe
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9783981080162
StatePublished - Jan 1 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010

ASJC Scopus subject areas

  • General Engineering


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