A novel low temperature integration of hybrid CMOS devices on flexible substrates

S. Gowrisanker, M. A. Quevedo-Lopez, H. N. Alshareef, B. E. Gnade, S. Venugopal, R. Krishna, K. Kaftanoglu, David Allee

Research output: Contribution to journalArticlepeer-review

32 Scopus citations


In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.

Original languageEnglish (US)
Pages (from-to)1217-1222
Number of pages6
JournalOrganic Electronics
Issue number7
StatePublished - Nov 2009


  • Flexible electronics
  • Hybrid CMOS
  • NAND gate
  • NOR gate

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Biomaterials
  • General Chemistry
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering


Dive into the research topics of 'A novel low temperature integration of hybrid CMOS devices on flexible substrates'. Together they form a unique fingerprint.

Cite this