A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells

Ankit Wagle, Gian Singh, Sunil Khatri, Sarma Vrudhula

Research output: Contribution to journalArticlepeer-review


In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells.

Original languageEnglish (US)
Pages (from-to)2968-2981
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number7
StatePublished - Jul 1 2022


  • Artificial neuron
  • flash
  • floating gate
  • high performance
  • low power
  • neural circuits
  • perceptron
  • threshold logic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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