A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking

Computer Science

• Application Specific Integrated Circuit 100%
• Power Optimization 100%
• Efficient Algorithm 50%
• Synthesis Tool 50%
• Benchmark Circuit 50%
• Conventional Method 50%
• Clock Skew 50%
• Hold Time Violation 50%
• Clocking Scheme 50%
• Completion Signal 50%

Keyphrases

• Power Optimization 100%
• Flip-flop 100%
• Area Optimization 100%
• Wirelength 42%
• UTBB FD-SOI 28%
• Publicly Available 14%
• Design Methodology 14%
• Synthesis Tool 14%
• Benchmark Circuits 14%
• Area Overhead 14%
• Clock Signal 14%
• D Flip-flop 14%
• Bulk CMOS 14%
• Energy Overhead 14%
• Clock Network 14%
• Edge Triggered 14%
• Clock Skew 14%
• Clocking Scheme 14%
• Hold Violation 14%

Engineering

• Application Specific Integrated Circuit 100%
• Conventional Method 50%
• Clock Signal 50%
• Hold Time 50%