A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking

A new design methodology for reducing the area and power of standard cell ASICs that uses a combination of differential flipflops and a method of deliberate clock-skewing, called local clocking (LC), is described. LC introduces clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: 1) the design of a new differential flipflop, referred to as KVFF, that is functionally identical to a double-latch edge-triggered D flipflop, but in addition, produces a completion signal that is a skewed version of its input clock, which is used to clock other flipflops and 2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. Furthermore, the area and power overhead of conventional methods of introducing skew, e.g., buffers, is eliminated. LC is shown to result in significant improvements in area, power, and wirelength for several, publicly available, benchmark circuits for 65 nm bulk CMOS and 28 nm FDSOI technologies. For 65 nm, the average improvement in area, power and wirelength were 27.7%, 13.4%, and 21.0%, respectively. For 28 nm FDSOI the average improvement in area, power, and wirelength were 20.0%, 10.5%, and 30.5%, respectively. In addition, this article demonstrates how LC can be used to eliminate hold time violations.