A multi-bit binary arithmetic coding technique

In this paper, we propose a new methodology for binary arithmetic coding which reduces the number of arithmetic operations significantly at the expense of a mild reduction in compression ratio. We achieve this by (i) considering a two symbol non-overlapping window and not coding the second symbol if both of them are Most Probable Symbols and (ii) moving the majority of computations to the Least Probable Symbol path. As a result, we reduce the additions/substractions required by 60-70%, with a loss of compression ratio of about 1-3% 3% compared to the Q-coder. This reduction in computational complexity makes the proposed technique particularly suitable for low-power VLSI implementation. In this paper, we have described the proposed algorithm and analyzed the results. We have also described a VLSI architecture capable of carrying out the algorithm.