A memory-efficient scheme for Address Lookup using Compact Prefix Tries

Anand Sarda, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper we present a new memory-efficient scheme for address lookup that exploits the caching support provided by general-purpose processors. We propose Compact Prefix Tries, in which prefixes occurring at multiple levels of a subtrie are compressed into a single node that fits in a single cache line. The scheme performs well in compressing dense as well as sparse tries. For an IP core router (Mae-West) database with 93354 prefixes, the simulation results for Compact Prefix Tries show up to 70% improvement in lookup performance and up to 33% reduction in memory when compared with LC-Tries. In fact, the entire forwarding table for Mae-West required only 829 KB space. Measurements for Compact Prefix Tries, when compared with most existing schemes, show better results in terms of memory usage as well as lookup speeds. Moreover, as the memory usage is significantly less and sparse tries with long paths can be compressed into only a few nodes, this scheme is particularly attractive for IPv6.

Original languageEnglish (US)
Title of host publicationGLOBECOM - IEEE Global Telecommunications Conference
Number of pages5
StatePublished - 2003
EventIEEE Global Telecommunications Conference GLOBECOM'03 - San Francisco, CA, United States
Duration: Dec 1 2003Dec 5 2003


OtherIEEE Global Telecommunications Conference GLOBECOM'03
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change


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