A low latency and low power indirect topology for on-chip communication

Usman Ali Gulzari, Sarzamin Khan, Muhammad Sajid, Sheraz Anjum, Frank Sill Torres, Hessam Sarjoughian, Abdullah Gani

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

Original languageEnglish (US)
Article numbere0222759
JournalPloS one
Issue number10
StatePublished - Oct 1 2019

ASJC Scopus subject areas

  • General


Dive into the research topics of 'A low latency and low power indirect topology for on-chip communication'. Together they form a unique fingerprint.

Cite this