A highly digital second-order oversampling TDC

Sanjeev Tannirkulam Chandrasekaran; Akshay Jayaraj; Mohammadhadi Danesh; Arindam Sanyal

doi:10.1109/LSSC.2018.2875818

A highly digital second-order oversampling TDC

Sanjeev Tannirkulam Chandrasekaran, Akshay Jayaraj, Mohammadhadi Danesh, Arindam Sanyal

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

A second-order, single loop Δ Σ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

Original language	English (US)
Article number	8490720
Pages (from-to)	114-117
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	1
Issue number	5
DOIs	https://doi.org/10.1109/LSSC.2018.2875818
State	Published - May 2018
Externally published	Yes

Keywords

Current-controlled oscillator
Delta-sigma
Noise shaping
Time-to-digital converter

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/LSSC.2018.2875818

Cite this

@article{19fcf202a395455b9f7604628857ba73,

title = "A highly digital second-order oversampling TDC",

abstract = "A second-order, single loop Δ Σ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.",

keywords = "Current-controlled oscillator, Delta-sigma, Noise shaping, Time-to-digital converter",

author = "Chandrasekaran, {Sanjeev Tannirkulam} and Akshay Jayaraj and Mohammadhadi Danesh and Arindam Sanyal",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

month = may,

doi = "10.1109/LSSC.2018.2875818",

language = "English (US)",

volume = "1",

pages = "114--117",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - A highly digital second-order oversampling TDC

AU - Chandrasekaran, Sanjeev Tannirkulam

AU - Jayaraj, Akshay

AU - Danesh, Mohammadhadi

AU - Sanyal, Arindam

PY - 2018/5

Y1 - 2018/5

N2 - A second-order, single loop Δ Σ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

AB - A second-order, single loop Δ Σ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

KW - Current-controlled oscillator

KW - Delta-sigma

KW - Noise shaping

KW - Time-to-digital converter

UR - http://www.scopus.com/inward/record.url?scp=85067958250&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85067958250&partnerID=8YFLogxK

U2 - 10.1109/LSSC.2018.2875818

DO - 10.1109/LSSC.2018.2875818

M3 - Article

AN - SCOPUS:85067958250

SN - 2573-9603

VL - 1

SP - 114

EP - 117

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

IS - 5

M1 - 8490720

ER -

A highly digital second-order oversampling TDC

Abstract

Keywords

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