A high-performance JPEG2000 architecture

Kishore Andra, Chaitali Chakrabarti, Tinku Acharya

Research output: Contribution to journalArticlepeer-review

129 Scopus citations


JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of the discrete wavelet transform, intra-subband bit-plane coding, and binary arithmetic coding in the standard. In this paper, we propose a system-level architecture capable of encoding and decoding the JPEG2000 core algorithm that has been defined in Part I of the standard. The key components include dedicated architectures for wavelet, bit plane, and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18-μ technology, is 3-mm square and the estimated frequency of operation is 200 MHz.

Original languageEnglish (US)
Pages (from-to)209-218
Number of pages10
JournalIEEE Transactions on Circuits and Systems for Video Technology
Issue number3
StatePublished - Mar 2003


  • Binary arithmetic coding
  • Bit-plane coding
  • JPEG2000
  • System architecture
  • Wavelet transform

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering


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