A digitally controlled DC-DC buck converter using frequency domain adcs

Hani Ahmad, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

The design of a 0.18-μm CMOS digital control architecture for a buck converter is presented. Several features are implemented. These include: 1) Frequency-domain digitization technique based on first-order non-feedback Sigma-Delta frequency Discriminators (NF-SDFD); 2) a robust arrangement for the feedback ADCs to guard against false output voltage variation due to temperature and process variation; 3) A new improved hybrid Digital Pulse Width Modulator (DPWM) architecture. The proposed system has additional attractive futures such simplicity, scalability, low power, close to all digital implementation in addition to its capability of satisfying tight regulation requirements for wide range of applications. An 8-bit ADC resolution is achieved with less than 110 μA current consumption. A 9-bit DPWM consumes around 370 μA . A 2% output voltage regulation accuracy is achieved with less than 10 mVpp ripple.

Original languageEnglish (US)
Title of host publicationAPEC 2010 - 25th Annual IEEE Applied Power Electronics Conference and Exposition
Pages1871-1874
Number of pages4
DOIs
StatePublished - 2010
Event25th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010 - Palm Springs, CA, United States
Duration: Feb 21 2010Feb 25 2010

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Other

Other25th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010
Country/TerritoryUnited States
CityPalm Springs, CA
Period2/21/102/25/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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