TY - JOUR
T1 - A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files
AU - Lee, Jongeun
AU - Shrivastava, Aviral
N1 - Funding Information:
Manuscript received March 7, 2009; revised November 10, 2009. Date of current version June 18, 2010. This research was partially funded by the National Science Foundation (NSF), under Grants CCF-0916652, IIP-0856090, and NSF I/UCRC for Embedded Systems, by Microsoft Research, by Raytheon, by the SFAz, by the Stardust Foundation, and by the Basic Science Research Program through the National Research Foundation of Korea (funded by MEST), under Grant 2010-0011534. The authors would like to thank all the members of the Compiler Microarchitecture Laboratory for their valuable support in this paper. This paper was recommended by Associate Editor S. A. Edwards.
PY - 2010/7
Y1 - 2010/7
N2 - For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.
AB - For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.
KW - Compiler-architecture hybrid
KW - embedded processor design
KW - energy
KW - partially protected register file (PPRF)
KW - register file vulnerability (RFV)
KW - reliability
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U2 - 10.1109/TCAD.2010.2049050
DO - 10.1109/TCAD.2010.2049050
M3 - Article
AN - SCOPUS:85008014183
SN - 0278-0070
VL - 29
SP - 1018
EP - 1027
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 7
ER -