A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

Jongeun Lee, Aviral Shrivastava

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.

Original languageEnglish (US)
Pages (from-to)1018-1027
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number7
StatePublished - Jul 2010


  • Compiler-architecture hybrid
  • embedded processor design
  • energy
  • partially protected register file (PPRF)
  • register file vulnerability (RFV)
  • reliability

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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