A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications

S. Shashidharan; W. Khalil; S. Chakraborty; Sayfe Kiaei; T. Copani; Bertan Bakkaloglu

doi:10.1109/RFIC.2010.5477249

A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications

S. Shashidharan, W. Khalil, S. Chakraborty, Sayfe Kiaei, T. Copani, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of -55dBc and a phase noise of -83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.

Original language	English (US)
Title of host publication	Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
Pages	409-412
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2010.5477249
State	Published - 2010
Event	2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010 - Anaheim, CA, United States Duration: May 23 2010 → May 25 2010

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Other

Other	2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
Country/Territory	United States
City	Anaheim, CA
Period	5/23/10 → 5/25/10

Keywords

Digital PLLs
Type-I PLLs
ΣΔ DACs

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/RFIC.2010.5477249

Cite this

Shashidharan, S., Khalil, W., Chakraborty, S., Kiaei, S., Copani, T., & Bakkaloglu, B. (2010). A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications. In Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010 (pp. 409-412). Article 10.1109/RFIC.2010.5477249 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2010.5477249

A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications. / Shashidharan, S.; Khalil, W.; Chakraborty, S. et al.
Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010. 2010. p. 409-412 10.1109/RFIC.2010.5477249 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shashidharan, S, Khalil, W, Chakraborty, S, Kiaei, S, Copani, T & Bakkaloglu, B 2010, A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications. in Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010., 10.1109/RFIC.2010.5477249, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, pp. 409-412, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010, Anaheim, CA, United States, 5/23/10. https://doi.org/10.1109/RFIC.2010.5477249

Shashidharan S, Khalil W, Chakraborty S, Kiaei S, Copani T, Bakkaloglu B. A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications. In Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010. 2010. p. 409-412. 10.1109/RFIC.2010.5477249. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC.2010.5477249

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abstract = "An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of -55dBc and a phase noise of -83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.",

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AB - An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of -55dBc and a phase noise of -83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.

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A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications

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