A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Keyphrases

• 65nm CMOS 14%
• Analog Circuits 100%
• Analog Devices 100%
• Analog Mixed-Signal 42%
• Array Design 14%
• Bitstream 14%
• CAD Tools 14%
• Cell Array 14%
• Circuit Emulation 100%
• Closed-loop 14%
• CMOS Technology 14%
• Configuration Memory 14%
• Current Reference 14%
• Design Cost 14%
• Design Methodology 14%
• Device Arrays 100%
• Digital Design 14%
• Dynamic Reconfiguration 14%
• Field Programmable Gate Arrays 28%
• Granularity 14%
• Hardware Testing 14%
• Input Offset 14%
• Measurement Results 14%
• Memory Programming 14%
• Mixed-signal Circuits 28%
• Offset Cancellation 14%
• Operational Amplifier 14%
• Programmable Analog 100%
• Programming Interface 14%
• Rapid Prototyping 28%
• Reconfigurable Analog 14%
• Reconfigurable Interconnect 14%
• Reconfiguration 28%
• Reference Filter 14%
• Representative Building 14%
• Scaled CMOS 14%
• Serial Programming 14%
• Shrinking Time 14%
• Synthesis Methods 14%
• Technology Mapping 14%
• Technology Node 14%
• Time to Market 14%
• Transistor Level 14%
• Voltage Reference 14%

Engineering

• Amplifier 33%
• Analog Circuit 100%
• Bitstream 33%
• Building Block 33%
• Cell Array 33%
• Closed Loop 33%
• Computer Aided Design 33%
• Current Reference 33%
• Dynamic Reconfiguration 33%
• Field Programmable Gate Arrays 66%
• Granularity 33%
• Interconnects 33%
• Nodes 33%
• Operational Amplifier 33%
• Rapid Prototyping 66%
• Reconfiguration 33%
• Signal Circuit 66%

Computer Science

• Analog Circuit 100%
• Building-Blocks 33%
• Computer Aided Design 33%
• Configuration Bit 33%
• Digital Design 33%
• Dynamic Reconfiguration 33%
• Field Programmable Gate Arrays 66%
• Granularity Level 33%
• Hardware Validation 33%
• Memory Programming 33%
• Operational Amplifier 33%
• Rapid Prototyping 66%
• Reconfiguration 33%
• Serial Programming 33%
• Technology Mapping 33%