@inproceedings{e386748cb17247e8b2bd3495e44db7ca,

title = "A 3GHz wideband ΣΔ fractional-N synthesizer with voltage-mode exponential CP-PFD",

abstract = "A 3GHz wideband ΣΔ fractional-N synthesizer with an exponential settling voltage-mode PFD is presented. The 1MHz band-width Type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode NMOS (follower) LDO based PFD-CP to reduce in-band quantization noise leakage by more than 13dB without the need for a noise suppression DAC. The PLL is fabricated on a 0.18μm CMOS process with less than 20-mA current consumption from 1.8-V power supply. The measured in-band phase noise at 100 kHz is -107dBc/Hz and out-of-band phase noise at 3 MHz is -130dBc/Hz. The PLL loop settling time for an accuracy of 0.1ppm and a frequency step of 45 MHz is less than 10μs.",

keywords = "Fractional-N frequency synthesizers, Phase noise, Quantization noise, Sigma-delta modulation",

author = "Hiva Hedayati and Bertan Bakkaloglu",

year = "2009",

doi = "10.1109/RFIC.2009.5135550",

language = "English (US)",

isbn = "9781424433780",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

pages = "325--328",

booktitle = "Proceedings of the 2009 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2009",

note = "2009 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2009 ; Conference date: 07-06-2009 Through 09-06-2009",

}