A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Jongwoo Lee; Joshua Kang; Sunghyun Park; Jae Sun Seo; Jens Anders; Jorge Guilherme; Michael P. Flynn

doi:10.1109/JSSC.2009.2028052

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Jongwoo Lee, Joshua Kang, Sunghyun Park, Jae Sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn

Research output: Contribution to journal › Article › peer-review

36 Scopus citations

Abstract

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm², and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

Original language	English (US)
Article number	18
Pages (from-to)	2755-2765
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2009.2028052
State	Published - Oct 2009
Externally published	Yes

Keywords

Compander
Logarithmic ADC
Pipeline ADC

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2009.2028052

Cite this

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title = "A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC",

abstract = "A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.",

keywords = "Compander, Logarithmic ADC, Pipeline ADC",

author = "Jongwoo Lee and Joshua Kang and Sunghyun Park and Seo, {Jae Sun} and Jens Anders and Jorge Guilherme and Flynn, {Michael P.}",

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language = "English (US)",

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AU - Lee, Jongwoo

AU - Kang, Joshua

AU - Park, Sunghyun

AU - Seo, Jae Sun

AU - Anders, Jens

AU - Guilherme, Jorge

AU - Flynn, Michael P.

PY - 2009/10

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AB - A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

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KW - Logarithmic ADC

KW - Pipeline ADC

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A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Abstract

Keywords

ASJC Scopus subject areas

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