A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC

Keyphrases

• 12-bit 33%
• 65nm CMOS 33%
• Calibration Method 33%
• Energy Efficiency 33%
• Frequency Dependence 33%
• High-resolution 33%
• Integration Time 33%
• Inter-stage Gain 66%
• Low Sampling Rate 33%
• Noise Shaping 66%
• Noise-shaping SAR 100%
• Passive Noise Reduction 66%
• Sampling Capacitor 33%
• SAR ADC 33%
• Simple Calibration 33%
• Successive Approximation Register 100%
• VCO Gain 33%
• VCO-based ADC 100%

Computer Science

• Approximation (Algorithm) 80%
• Energy Efficiency 20%
• Integration Time 20%
• noise shaping 100%
• Pipelining 20%

Physics

• Energy Efficiency 50%
• High Resolution 50%
• Synthetic Aperture Radar 100%