A 0.7-V 0.6- μw 100-kS/s Low-Power SAR ADC with Statistical Estimation-Based Noise Reduction

Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun

Research output: Contribution to journalArticlepeer-review

54 Scopus citations


This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relatively low resolution digital-to-analog converter (DAC). The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least significant bit (LSB) comparisons. Three estimation schemes are studied and the optimal Bayes estimator is chosen for a prototype 11-b ADC in 65-nm CMOS. The measured SNR is improved by 7 dB with the proposed noise reduction technique. Overall, it achieves 10.5-b effective number of bits while operating at 100 kS/s and consuming 0.6μW from a 0.7-V power supply.

Original languageEnglish (US)
Article number7857744
Pages (from-to)1388-1398
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - May 2017
Externally publishedYes


  • Analog-to-digital converter (ADC)
  • comparator noise
  • data converter
  • high resolution
  • low power
  • statistical estimation
  • successive approximation register (SAR)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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