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A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

  • Yong Liu
  • , Ping Hsuan Hsieh
  • , Seongwon Kim
  • , Jae Sun Seo
  • , Robert Montoye
  • , Leland Chang
  • , Jose Tierno
  • , Daniel Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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