TY - GEN
T1 - A 0.13 μm low-power race-free programmable logic array
AU - Samson, Giby
AU - Clark, Lawrence T.
PY - 2006
Y1 - 2006
N2 - A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.
AB - A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.
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U2 - 10.1109/CICC.2006.320899
DO - 10.1109/CICC.2006.320899
M3 - Conference contribution
AN - SCOPUS:39049095143
SN - 1424400767
SN - 9781424400768
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 313
EP - 316
BT - Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
T2 - IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Y2 - 10 September 2006 through 13 September 2006
ER -