TY - GEN
T1 - 3D ensemble Monte Carlo device simulations of random trap induced degradation in drain current and in threshold voltage in the presence of random dopant distributions for 45 nm gate length MOSFETs
AU - Ashraf, Nabil
AU - Vasileska, Dragica
PY - 2010/12/1
Y1 - 2010/12/1
N2 - We investigate the influence of a single trap and two traps in close proximity located at the semiconductor/oxide interface (positioned in the middle portion of the gate width and gradually moved from the source end to the drain end of the channel). We find that when the trap is located at the source end of the channel, the threshold voltage and the magnitude of the drain current are dominated by the potential barrier created by the negatively charged (repulsive) trap. When the trap is positioned at the drain end of the channel, the barrier effect on carrier transport is smaller and screening (for small drain bias) and the absence of screening (at large drain bias due to the presence of pinch-off region) determine whether current will not be degraded or will be degraded, respectively. Additionally, the simulations reveal that the degradation characteristics are worse for the case of two traps in close proximity when compared to a single trap case at the same relative trap position because two traps in close proximity generate higher Coulomb potential barrier in the vicinity of the trap's interaction zone with the carriers, impending transport of carriers in the channel from source to drain region of the MOSFET. Twenty random dopant configurations are used for each trap position. We find that this size of the statistical sample is sufficient to give reliable and physically meaningful results.
AB - We investigate the influence of a single trap and two traps in close proximity located at the semiconductor/oxide interface (positioned in the middle portion of the gate width and gradually moved from the source end to the drain end of the channel). We find that when the trap is located at the source end of the channel, the threshold voltage and the magnitude of the drain current are dominated by the potential barrier created by the negatively charged (repulsive) trap. When the trap is positioned at the drain end of the channel, the barrier effect on carrier transport is smaller and screening (for small drain bias) and the absence of screening (at large drain bias due to the presence of pinch-off region) determine whether current will not be degraded or will be degraded, respectively. Additionally, the simulations reveal that the degradation characteristics are worse for the case of two traps in close proximity when compared to a single trap case at the same relative trap position because two traps in close proximity generate higher Coulomb potential barrier in the vicinity of the trap's interaction zone with the carriers, impending transport of carriers in the channel from source to drain region of the MOSFET. Twenty random dopant configurations are used for each trap position. We find that this size of the statistical sample is sufficient to give reliable and physically meaningful results.
KW - Coulomb potential well due to one trap and two traps
KW - Fluctuation in drain current and threshold voltage
KW - Random dopant fluctuation (RDF)
KW - Random telegraph signal/noise (RTS/RTN)
UR - http://www.scopus.com/inward/record.url?scp=78751679957&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78751679957&partnerID=8YFLogxK
U2 - 10.1109/IWCE.2010.5677974
DO - 10.1109/IWCE.2010.5677974
M3 - Conference contribution
AN - SCOPUS:78751679957
SN - 9781424493845
T3 - 2010 14th International Workshop on Computational Electronics, IWCE 2010
SP - 231
EP - 234
BT - 2010 14th International Workshop on Computational Electronics, IWCE 2010
T2 - 2010 14th International Workshop on Computational Electronics, IWCE 2010
Y2 - 26 October 2010 through 29 October 2010
ER -