In-memory computing (IMC) has emerged as a promising technique for enhancing energy efficiency of deep neural networks (DNNs). While embedded nonvolatile memory, such as resistive RAM (RRAM) is a good alternative to SRAM/DRAM for IMC owing to high density, low leakage, and nondestructive read, most prior works have not demonstrated using multilevel RRAM devices for array-level IMC operations. In this letter, we present an IMC prototype with 2-bit-per-cell RRAM devices for area-/energy-efficient DNN inference. Optimizations on four-level conductance distribution and peripheral circuits with input-splitting scheme have been performed, enabling high DNN accuracy and low area/energy consumption. The prototype chip that monolithically integrated 90-nm CMOS and 2-bit-per- cell RRAM array achieves 87% (83%) CIFAR-10 accuracy and 25 (51) TOPS/W energy efficiency at 1.2 V (0.9 V) supply. At 1.2 V, a stable accuracy of 87% is maintained throughout 108 h.
- Deep neural networks (DNNs)
- in-memory computing (IMC)
- multilevel cell
ASJC Scopus subject areas
- Electrical and Electronic Engineering